Exemplary embodiments of the present invention relate to a filter design technology, and more particularly, to a filter circuit and an integrated circuit including the same.
According to an example, a moving average filter calculates an average value of a plurality of input signals and outputs the average value as an output signal. The moving average filter removes high frequency elements included in the input signals by the averaging operation. Thus, the moving average filter is used as a low pass filter and to average the previous output signals in a circular filtering algorithm, where an infinite impulse response of the moving average filter is obtained.
FIG. 1 is a diagram illustrating a conventional filter circuit.
As shown in FIG. 1, the conventional filter circuit includes a plurality of shifting units 110, 111A to 115A, and 1118 to 115B, a first selecting unit 120 and a second selecting unit 130.
Hereinafter, an integration method filter, a proportional method filter, and a “depth” of the filter are described.
The integration method filter generates an output signal OU or OUT2 when a difference between a number of input times K1 of a first input signal IN1 and a number of input times K2 of a second input signal IN2 becomes a first desired value. More particularly, when K1 is larger than K2 by the first value, the first output signal OUT1 is generated, and when K2 is larger than K1 by the first value, the second output signal OUT2 is generated.
The proportional method filter generates an output signal OUT1 or OUT2 according to a first consecutive input times L1 of the first input signal IN1 and a second consecutive input times L2 of the second input signal IN2. More particularly, when L1 becomes a second desired value, the first output signal OUT1 is generated, and when L2 becomes the second value, the second output signal OUT2 is generated.
The “depth” of the filter refers to the first value used in the integration method filter or the second value used in the proportional method filter.
Referring to FIG. 1, operations of the integration method filter are as follows.
When the filter circuit is initialized, ‘1’ is stored in a center shifting unit 110 and ‘0’s are stored in other shifting units (111A to 115A and 111B to 115B).
When the first input signal IN1 is inputted, the plurality of shifting units 110, 111A to 115A, and 111B to 115B shift the stored value in a first direction 101, and when the second input signal IN2 is inputted, the plurality of shifting units 110, 111A to 115A, and 111B to 115B shift the stored value in a second direction 102.
The first selecting unit 120 selects one of the output signals UOUT0 to UOUT4 from the upper shifting units 111A to 115A) as a first output signal OUT1 based on the depth of the filter. The second selecting unit 130 selects one of the output signals DOUT0 to DOUT4 from the lower shifting units 111B to 115B) as a second output signal OUT2 based on the depth of the filter.
The first and second selecting units 120 and 130 each select an output signal in response to a depth information SEL. The depth information SEL may be a digital signal of at least 1 data bit that represents a depth of a filter circuit, where the depth is not greater than the maximum value of the depth.
For example, when the depth is 3, the first selecting unit 120 selects a third upper output signal UOUT<2> as the first output signal OUT1, and the second selecting unit 130 selects a third lower output signal DOUT<2> as the second output signal OUT2. When a value obtained by subtracting K2 from K1 becomes 3, the third upper output signal UOUT<2> is ‘1’, and the first output signal OUT1 is activated. When a value obtained by subtracting K1 from K2 becomes 3, the third lower output signal DOUT<2> in the second direction 102 is ‘1’, and the second output signal OUT2 is activated.
The first selecting unit 120 may be formed of a multiplexer that selects one of the output signals UOUT<0> to UOUT<4> as the first output signal OUT1 in response to the depth information SEL. The second selecting unit 130 may be formed to have the same structure as the first selecting unit 120.
The filter circuit removes noise included in the input signals IN1 and IN2 through the above operations. Even if the second input signal is inputted while the first input signals IN1 are consecutively inputted, an output is not outputted unless a difference between K2 and K1 is equal to the depth of the filter. Thus, noise may be removed. That is, the filter circuit may remove noise unless the same noise occurs more than a desired number of times.
The maximum of the depth is determined by the number of shifting units 111A to 115A connected in the first direction 101 or the number of shifting units 111B to 115B connected in the second direction 102. As shown in FIG. 1, the number of shifting units connected in the first direction 101 or the number of shifting units connected in the second direction is 5, and the maximum of the depth is 5. Therefore, the depth of the filter may be set from 1 to 5.
However, the first selecting unit 120 and the second selecting unit 130 are formed of multiplexer. As the maximum of the depth is increased, the number of multiplexer's inputs is increased. Thus, the filter circuit becomes complex and occupies large area, and output load thereof is increased due to a numbers of logic gate stages. As output load increase, the level of the output signal OUT1 or OUT2 decrease. Therefore, the size and the current consumption of a buffer (not shown in FIG. 1) may increase to compensate the level of the output signal OUT1 or OUT2.